1. Field of the Invention
The present invention relates generally to semiconductor device fabrication, and more specifically to a method of using design signature analytics for improving lithographic process of manufacturing semiconductor device.
2. Description of Related Arts
Semiconductor devices are manufactured by fabricating many layers of circuit patterns on wafers to form massive transistors for integration as complicated circuits. In the manufacturing flow of semiconductor devices, lithography process is responsible for transferring the circuit patterns created by circuit designers onto wafers.
Photomasks with opaque and clear patterns according to the circuit patterns are used for patterning device layers on wafers. Distortion of the patterns can result from the effect of the neighboring patterns on the photomask and optical diffraction. Optical proximity correction (OPC) and lithographic process check (LPC) are important techniques commonly used for correcting the pattern distortion for design for manufacturability (DFM).
FIG. 1 shows a typical flow in initial setup and on-going tune-up for optimizing the lithography process of manufacturing semiconductor devices. Circuit patterns for manufacturing the photomask of a device layer is described in a design data file generated by the circuit designer shown in block 101 that contains design data in GDS or OASIS format. The design data may be random circuit patterns generated from random layout generator (RLG) or product qualification vehicle (PQV) from vendors or pilot customers. Block 102 shows OPC creation that generates the required OPC by using the OPC model and recipe and DFM model and recipe that include additional manufacturing effects other than OPC from block 103. After OPC creation, Block 102 also performs OPC verification based on OPC model and LPC verification based on DFM model.
OPC and LPC verification also predicts potential yield limiting hot spots caused by specific layout and patterns. As shown in block 104, wafers manufactured by the lithography process using the OPC photomask are examined by either optical or e-beam inspector and metrology machine to detect defects and measure critical dimensions in the hot spots. Inspection and metrology data of the predicted hot spots are fed back to block 103 to tune the models and recipes of OPC and DFM.
As technology advances to 20nm and beyond, designs are scaled down and the scaling down to small geometries has resulted in many systematic manufacturing variations that limit manufacturing yield more than the random variations. The interaction of small geometries within the optical proximity and the lithography process creates highly nonlinear systematic variations that are difficult or impossible to model in OPC or DFM. As a result, many manufacturing critical hot spots cannot be predicted and uncovered by the OPC and LPC verification in the setup and tuning flow shown in FIG. 1. Consequentially, these uncovered manufacturing critical hot spots may lead to catastrophic yield loss in mass production of the semiconductor device.